This adds support for the XVentanaCondOps custom extension (vendor-defined by Ventana Micro Systems), which is documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
Given that the CUSTOM-3 opcode space is shared between vendors, these are implemented as overlapping patterns and use the newly introduced predicate-function infrastructure to further qualify the decode. Signed-off-by: Philipp Tomsich <[email protected]> --- target/riscv/cpu.c | 3 ++ target/riscv/cpu.h | 3 ++ target/riscv/insn32.decode | 6 +++ .../insn_trans/trans_xventanacondops.inc | 39 +++++++++++++++++++ target/riscv/translate.c | 9 +++++ 5 files changed, 60 insertions(+) create mode 100644 target/riscv/insn_trans/trans_xventanacondops.inc diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e322e729d2..0355ca35e6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -645,6 +645,9 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_xventanacondops, false), + /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc10f27093..283e45755a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -318,6 +318,9 @@ struct RISCVCPU { bool ext_zfh; bool ext_zfhmin; + /* Vendor-specific custom extensions */ + bool ext_xventanacondops; + char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 8617307b29..ef7372a59d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -784,3 +784,9 @@ fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm + +# *** RV64 Custom-3 Extension *** +{ + vt_maskc 0000000 ..... ..... 110 ..... 1111011 @r |has_xventanacondops_p + vt_maskcn 0000000 ..... ..... 111 ..... 1111011 @r |has_xventanacondops_p +} \ No newline at end of file diff --git a/target/riscv/insn_trans/trans_xventanacondops.inc b/target/riscv/insn_trans/trans_xventanacondops.inc new file mode 100644 index 0000000000..b8a5d031b5 --- /dev/null +++ b/target/riscv/insn_trans/trans_xventanacondops.inc @@ -0,0 +1,39 @@ +/* + * RISC-V translation routines for the XVentanaCondOps extension. + * + * Copyright (c) 2021-2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +static bool gen_condmask(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_vt_maskc(DisasContext *ctx, arg_r *a) +{ + return gen_condmask(ctx, a, TCG_COND_NE); +} + +static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a) +{ + return gen_condmask(ctx, a, TCG_COND_EQ); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5df6c0d800..121c5605ea 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -115,6 +115,14 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa_ext & ext; } +#define MATERIALISE_EXT_PREDICATE(ext) \ + static inline bool has_ ## ext ## _p(DisasContext *ctx) \ + { \ + return RISCV_CPU(ctx->cs)->cfg.ext_ ## ext ; \ + } + +MATERIALISE_EXT_PREDICATE(xventanacondops); + #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -651,6 +659,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" +#include "insn_trans/trans_xventanacondops.inc" /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" -- 2.33.1
