On Thu, Jan 6, 2022 at 7:55 AM Alistair Francis <alistair.fran...@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.fran...@wdc.com> > > This is a few patches to cleanup some RISC-V hardware and mark the > Hyperisor extension as non experimental. > > v4: > - Resend > v3: > - Drop some patches > - Few small fixes from reviews > v2: > - Add some more fixes > - Address review comments > > Alistair Francis (8): > hw/intc: sifive_plic: Add a reset function > hw/intc: sifive_plic: Cleanup the write function > hw/intc: sifive_plic: Cleanup the read function > hw/intc: sifive_plic: Cleanup remaining functions > target/riscv: Mark the Hypervisor extension as non experimental > target/riscv: Enable the Hypervisor extension by default > hw/riscv: Use error_fatal for SoC realisation > hw/riscv: virt: Allow support for 32 cores
Thanks! Applied to riscv-to-apply.next Alistair > > include/hw/riscv/virt.h | 2 +- > hw/intc/sifive_plic.c | 254 +++++++++++-------------------------- > hw/riscv/microchip_pfsoc.c | 2 +- > hw/riscv/opentitan.c | 2 +- > hw/riscv/sifive_e.c | 2 +- > hw/riscv/sifive_u.c | 2 +- > target/riscv/cpu.c | 2 +- > 7 files changed, 82 insertions(+), 184 deletions(-) > > -- > 2.31.1 > >
