This series of patches provides partial 128-bit support for the riscv target architecture, namely RVI and RVM, with very minimal csr support.
Per Richard suggestions, this v4 makes the accesses to the gprs safer and cleaner, which paves the way to a more integrated 64/128 version. It also uses locals for load/store/div/rem helpers, cleans out the 128-bit div/rem code, corrects numerous bugs and performs optimizations on shifts and mults, all pointed out by Richard. It finally withdraws the change in page size and the vm schemes we previously introduced. However, there is still some work: - 128-bit atomic align accesses: for now, mttcg is disabled, my understanding there is, to say the least, low - full 64/128 bit integration to remove the need for a 128-bit executable. There are places in which I do not yet see clearly how to handle this. Frédéric Pétrot (17): exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO qemu/int128: addition of a few 128-bit operations target/riscv: additional macros to check instruction support target/riscv: separation of bitwise logic and aritmetic helpers target/riscv: array for the 64 upper bits of 128-bit registers target/riscv: setup everything so that riscv128-softmmu compiles target/riscv: moving some insns close to similar insns target/riscv: accessors to registers upper part and 128-bit load/store target/riscv: support for 128-bit bitwise instructions target/riscv: support for 128-bit U-type instructions target/riscv: support for 128-bit shift instructions target/riscv: support for 128-bit arithmetic instructions target/riscv: support for 128-bit M extension target/riscv: adding high part of some csrs target/riscv: helper functions to wrap calls to 128-bit csr insns target/riscv: modification of the trans_csrxx for 128-bit support target/riscv: actual functions to realize crs 128-bit insns configs/devices/riscv128-softmmu/default.mak | 17 + configs/targets/riscv128-softmmu.mak | 6 + include/disas/dis-asm.h | 1 + include/exec/memop.h | 13 +- include/hw/riscv/sifive_cpu.h | 3 + include/qemu/int128.h | 26 + target/arm/translate-a32.h | 4 +- target/riscv/cpu-param.h | 5 + target/riscv/cpu.h | 28 + target/riscv/cpu_bits.h | 1 + target/riscv/helper.h | 9 + target/riscv/insn16.decode | 27 +- target/riscv/insn32.decode | 25 + disas/riscv.c | 5 + target/arm/translate-a64.c | 8 +- target/arm/translate-neon.c | 6 +- target/arm/translate-sve.c | 2 +- target/arm/translate-vfp.c | 8 +- target/arm/translate.c | 2 +- target/ppc/translate.c | 24 +- target/riscv/cpu.c | 31 +- target/riscv/csr.c | 191 ++++- target/riscv/gdbstub.c | 8 + target/riscv/m128_helper.c | 109 +++ target/riscv/machine.c | 22 + target/riscv/op_helper.c | 44 ++ target/riscv/translate.c | 252 +++++- target/sparc/translate.c | 4 +- util/int128.c | 218 ++++++ target/ppc/translate/fixedpoint-impl.c.inc | 20 +- target/ppc/translate/fp-impl.c.inc | 4 +- target/ppc/translate/vsx-impl.c.inc | 4 +- target/riscv/insn_trans/trans_rvb.c.inc | 48 +- target/riscv/insn_trans/trans_rvd.c.inc | 12 +- target/riscv/insn_trans/trans_rvf.c.inc | 6 +- target/riscv/insn_trans/trans_rvi.c.inc | 770 ++++++++++++++++--- target/riscv/insn_trans/trans_rvm.c.inc | 197 ++++- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 10 +- tcg/i386/tcg-target.c.inc | 4 +- tcg/mips/tcg-target.c.inc | 4 +- tcg/ppc/tcg-target.c.inc | 8 +- tcg/riscv/tcg-target.c.inc | 6 +- tcg/s390x/tcg-target.c.inc | 10 +- target/riscv/Kconfig | 3 + target/riscv/meson.build | 1 + util/meson.build | 1 + 47 files changed, 1925 insertions(+), 284 deletions(-) create mode 100644 configs/devices/riscv128-softmmu/default.mak create mode 100644 configs/targets/riscv128-softmmu.mak create mode 100644 target/riscv/m128_helper.c create mode 100644 util/int128.c -- 2.33.0
