On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson < [email protected]> wrote:
> On 10/14/21 11:54 PM, [email protected] wrote: > > From: Chih-Min Chao<[email protected]> > > > > The sNaN propagation behavior has been changed since > > cd20cee7 inhttps://github.com/riscv/riscv-isa-manual > > > > Signed-off-by: Chih-Min Chao<[email protected]> > > --- > > target/riscv/fpu_helper.c | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > > index 8700516a14c..1472ead2528 100644 > > --- a/target/riscv/fpu_helper.c > > +++ b/target/riscv/fpu_helper.c > > @@ -174,14 +174,14 @@ uint64_t helper_fmin_s(CPURISCVState *env, > uint64_t rs1, uint64_t rs2) > > { > > float32 frs1 = check_nanbox_s(rs1); > > float32 frs2 = check_nanbox_s(rs2); > > - return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status)); > > + return nanbox_s(float32_minnum_noprop(frs1, frs2, &env->fp_status)); > > } > > Don't you need to conditionalize behaviour on the isa revision? > > I will pick the right API based on CPU privilege spec version. Thanks, Frank Chang > > r~ >
