On Thu, 16 Sept 2021 at 22:49, Alistair Francis
<[email protected]> wrote:
>
> From: Alistair Francis <[email protected]>
>
> The following changes since commit d1fe59377bbbf91dfded1f08ffe3c636e9db8dc0:
>
> Merge remote-tracking branch
> 'remotes/vivier2/tags/trivial-branch-for-6.2-pull-request' into staging
> (2021-09-16 16:02:31 +0100)
>
> are available in the Git repository at:
>
> [email protected]:alistair23/qemu.git tags/pull-riscv-to-apply-20210917
>
> for you to fetch changes up to c14620db9b66de88bb4fef1d0cfc283bb3d53f85:
>
> hw/riscv: opentitan: Correct the USB Dev address (2021-09-17 07:43:55 +1000)
>
> ----------------------------------------------------------------
> Second RISC-V PR for QEMU 6.2
>
> - ePMP CSR address updates
> - Convert internal interrupts to use QEMU GPIO lines
> - SiFive PWM support
> - Support for RISC-V ACLINT
> - SiFive PDMA fixes
> - Update to u-boot instructions for sifive_u
> - mstatus.SD bug fix for hypervisor extensions
> - OpenTitan fix for USB dev address
>
Hi; this fails to build on clang:
../../target/riscv/cpu_helper.c:109:64: error: implicit conversion
from 'unsigned long long' to 'target_ulong' (aka 'unsigned int')
changes value from 9223372036854775808 to 0
[-Werror,-Wconstant-conversion]
target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
~~ ^~~~~~~~~~~~
../../target/riscv/cpu_bits.h:362:29: note: expanded from macro 'MSTATUS64_SD'
#define MSTATUS64_SD 0x8000000000000000ULL
^~~~~~~~~~~~~~~~~~~~~
1 error generated.
thanks
-- PMM
