On Thu, Sep 2, 2021 at 7:51 PM Anup Patel <anup.pa...@wdc.com> wrote: > > We define a CPU feature for AIA CSR support in RISC-V CPUs which > can be set by machine/device emulation. The RISC-V CSR emulation > will also check this feature for emulating AIA CSRs. > > Signed-off-by: Anup Patel <anup.pa...@wdc.com> > --- > target/riscv/cpu.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >
Reviewed-by: Bin Meng <bmeng...@gmail.com>
