Re: [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

[Richard Henderson]

On 8/18/21 10:32 AM, Philipp Tomsich wrote:
+++ b/target/riscv/cpu.h
@@ -67,7 +67,6 @@
  #define RVS RV('S')
  #define RVU RV('U')
  #define RVH RV('H')
-#define RVB RV('B')

This patch does not compile by itself, because RVB is still used in 
insn_trans/trans_rvb.c.inc.


r~