Re: [PATCH for-6.2 03/34] target/arm: Fix MVE VSLI by 0 and VSRI by

[Richard Henderson]

On 7/13/21 6:36 AM, Peter Maydell wrote:

          if (shift == 0 || shift == ESIZE * 8) {                         \
              /*                                                          \
               * Only VSLI can shift by 0; only VSRI can shift by <dt>.   \
               * The generic logic would give the right answer for 0 but  \
-             * fails for <dt>.                                          \
+             * fails for <dt>. In both cases, we must not shift the     \
+             * input but just copy it to the destination, honouring     \
+             * the predicate mask.                                      \
               */                                                         \
+            for (e = 0; e < 16 / 8; e++, mask >>= 8) {                  \
+                mergemask(&d[H8(e)], m[H8(e)], mask);                   \
+            }                                                           \
              goto done;                                                  \
          }                                                               \

VSLI is d = op1 << shift | (d & ~(-1 << shift))

for shift = 0 does result in d = op1.

However,

VRSI is d = op1 >> shift | (d & ~(-1 >> shift))

for shift = 32 results in d = d.


r~