riscv: Expose interrupt pending bits as GPIO lines

Bin Meng Thu, 15 Jul 2021 01:23:05 -0700

On Wed, Jul 14, 2021 at 3:24 PM Alistair Francis
<[email protected]> wrote:
>
> Expose the 12 interrupt pending bits in MIP as GPIO lines.
>
> Signed-off-by: Alistair Francis <[email protected]>
> Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
> Reviewed-by: Richard Henderson <[email protected]>
> Reviewed-by: Bin Meng <[email protected]>
> ---
>  target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>


Tested-by: Bin Meng <[email protected]>

Re: [PATCH v2 1/5] target/riscv: Expose interrupt pending bits as GPIO lines

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