Re: [PATCH 1/9] target/mips: Do not abort on invalid instruction

[Richard Henderson]

On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:

On real hardware an invalid instruction doesn't halt the world,
but usually triggers a RESERVED INSTRUCTION exception.
TCG guest code shouldn't abort QEMU anyway.

Signed-off-by: Philippe Mathieu-Daudé<f4...@amsat.org>
---
  target/mips/tcg/translate.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>