On 6/10/21 12:58 AM, LIU Zhiwei wrote:
include/tcg/tcg-op-gvec.h | 9 ++ tcg/tcg-op-gvec.c | 28 +++++++
Again, should be split out, with a Reviewed-by: Richard Henderson <[email protected]> r~
- [PATCH v2 00/37] target/riscv: support packed extension ... LIU Zhiwei
- [PATCH v2 01/37] target/riscv: implementation-defin... LIU Zhiwei
- [PATCH v2 02/37] target/riscv: Make the vector help... LIU Zhiwei
- [PATCH v2 04/37] target/riscv: 8-bit Addition &... LIU Zhiwei
- Re: [PATCH v2 04/37] target/riscv: 8-bit Additi... Richard Henderson
- [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift In... LIU Zhiwei
- Re: [PATCH v2 05/37] target/riscv: SIMD 16-bit ... Richard Henderson
- [PATCH v2 03/37] target/riscv: 16-bit Addition &... LIU Zhiwei
- Re: [PATCH v2 03/37] target/riscv: 16-bit Addit... Richard Henderson
- [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply... LIU Zhiwei
- [PATCH v2 06/37] target/riscv: SIMD 8-bit Shift Ins... LIU Zhiwei
- [PATCH v2 08/37] target/riscv: SIMD 8-bit Compare I... LIU Zhiwei
- [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare ... LIU Zhiwei
- [PATCH v2 13/37] target/riscv: 8-bit Unpacking Inst... LIU Zhiwei
- [PATCH v2 10/37] target/riscv: SIMD 8-bit Multiply ... LIU Zhiwei
- [PATCH v2 12/37] target/riscv: SIMD 8-bit Miscellan... LIU Zhiwei
- [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Mul... LIU Zhiwei
