From: Ilya Leoshkevich <[email protected]> tb_gen_code() assumes that tb->size must never be zero, otherwise it may produce spurious exceptions. For ARM this may happen when creating a translation block for the commpage.
Fix by pretending that commpage translation blocks have at least one instruction. Signed-off-by: Ilya Leoshkevich <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Cornelia Huck <[email protected]> --- target/arm/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 43ff0d4b8ac2..c8dbb03d6db8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9097,6 +9097,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) unsigned int insn; if (arm_pre_translate_insn(dc)) { + dc->base.pc_next += 4; return; } @@ -9166,6 +9167,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) bool is_16bit; if (arm_pre_translate_insn(dc)) { + dc->base.pc_next += 2; return; } -- 2.30.2
