On 4/7/21 6:57 PM, Taylor Simpson wrote:
+static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
+{
+ /*
+ * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual
+ *
+ * The "I" value from a modifier register is divided into two pieces
+ * LSB bits 23:17
+ * MSB bits 31:28
+ * The value is signed, so we do a sign extension
+ *
+ * At the end we shift the result according to the shift argument
+ */
+ TCGv msb = tcg_temp_new();
+ TCGv lsb = tcg_temp_new();
+
+ tcg_gen_extract_tl(lsb, val, 17, 7);
+ tcg_gen_extract_tl(msb, val, 28, 4);
+ tcg_gen_movi_tl(result, 0);
+ tcg_gen_deposit_tl(result, result, lsb, 0, 7);
+ tcg_gen_deposit_tl(result, result, msb, 7, 4);
+ tcg_gen_shli_tl(result, result, 21);
+ tcg_gen_sari_tl(result, result, 21);
I gave you the 3 line version last time:
(1) shift msb, signed, into position at bit 7,
(2) extract lsb,
(3) deposit into msb, overwriting the low 7 bits.
And anyway, those last two lines are tcg_gen_sextract.
With that changed,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
