Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions

[LIU Zhiwei]

On 2021/2/13 2:03, Richard Henderson wrote:
On 2/12/21 7:02 AM, LIU Zhiwei wrote:
+    if (a->rd && a->rs1 && a->rs2) {
+#ifdef TARGET_RISCV64
+        f64(vece, offsetof(CPURISCVState, gpr[a->rd]),
+            offsetof(CPURISCVState, gpr[a->rs1]),
+            offsetof(CPURISCVState, gpr[a->rs2]),
+            8, 8);
+#else
This is not legal tcg.
You cannot reference as memory anything which has an associated tcg_global_mem.
Thanks.

Do you mean referring  a global TCGTemp as memory will cause not 
consistent between TCGContext::temps and
CPUArchState field?

Zhiwei
  Which is true for all of the gprs -- see riscv_translate_init.


r~