On 21-01-27 22:21:04, Igor Mammedov wrote: > On Wed, 27 Jan 2021 13:11:16 -0800 > Ben Widawsky <[email protected]> wrote: > > > On 21-01-27 22:03:12, Igor Mammedov wrote: > > > On Tue, 5 Jan 2021 08:53:15 -0800 > > > Ben Widawsky <[email protected]> wrote: > > > > > > > A CXL memory device (AKA Type 3) is a CXL component that contains some > > > > combination of volatile and persistent memory. It also implements the > > > > previously defined mailbox interface as well as the memory device > > > > firmware interface. > > > > > > > > The following example will create a 256M device in a 512M window: > > > > > > > > -object > > > > "memory-backend-file,id=cxl-mem1,share,mem-path=cxl-type3,size=512M" > > > > -device "cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,size=256M" > > > > > > I'd expect whole backend used by frontend, so one would not need "size" > > > property > > > on frontend (like we do with memory devices). > > > So question is why it partially uses memdev? > > > > A CXL memory device may participate in an interleave set. In such a case, it > > would be < the total size of the memory window. > > > > This isn't implemented in the code yet, but it is planned. > > could you add here how it supposed to look like CLI interface wise? > > also see other questions below. >
My mistake on the other questions. I forked another thread for those. Interleave is still being fleshed out. But generally to set up a 512M address range interleaves across 2 devices, each 256M, and each connected to a root port on the host bridge: # Memory backend -object memory-backend-file,id=cxl-mem1,share,mem-path=cxl-type3,size=512M # Host Bridge -device pxb-cxl id=cxl.0,bus=pcie.0,bus_nr=52,uid=0 len-window-base=1,window-base[0]=0x4c0000000 memdev[0]=cxl-mem1 # 2 root ports -device cxl-rp,id=rp0,bus=cxl.0,addr=0.0,chassis=0,slot=0,memdev=cxl-mem1 -device cxl-rp,id=rp1,bus=cxl.0,addr=0.1,chassis=0,slot=1,memdev=cxl-mem1 # 2 PMEM devices -device cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0,size=256M -device cxl-type3,bus=rp1,memdev=cxl-mem1,id=cxl-pmem1,size=256M
