On Thu, 14 Jan 2021 at 12:50, Peter Maydell <[email protected]> wrote:
>
> On Thu, 14 Jan 2021 at 00:04, Andrew Jones <[email protected]> wrote:
> >
> > On Wed, Jan 13, 2021 at 10:30:47AM +0300, Maxim Uvarov wrote:
> > > - the same size for secure and non secure gpio. Arm doc says that
> > > secure memory is also split on 4k pages. So one page here has to be
> > > ok.
> >
> > To be clear, does that means 4k pages must be used? I'm not concerned
> > with the size, but the alignment. If it's possible to use larger page
> > sizes with secure memory, then we need to align to the maximum page
> > size that may be used.
>
> I think we should just align on 64K, to be more future-proof.
> Even if secure software today uses 4K pages, it doesn't hurt
> to align the device such that some hypothetical future 64K
> page using secure software can use it.
>
> thanks
> -- PMM
Does that mean that in that case you need all regions to be 64k
aligned? I mean secure and non-secure.
Has anybody tested 64k pages under qemu?
[VIRT_GIC_V2M] = { 0x08020000, 0x00001000 }
[VIRT_UART] = { 0x09000000, 0x00001000 },
[VIRT_RTC] = { 0x09010000, 0x00001000 },
[VIRT_GPIO] = { 0x09030000, 0x00001000 },
[VIRT_SECURE_GPIO] = { 0x09031000, 0x00001000 },
[VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
Maxim.
