[PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

[frank . chang]

From: Frank Chang <frank.ch...@sifive.com>

Signed-off-by: Frank Chang <frank.ch...@sifive.com>
---
 target/riscv/csr.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 28c1ce7928a..176010674e8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -301,7 +301,7 @@ static int write_vxrm(CPURISCVState *env, int csrno, 
target_ulong val)
     if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
         return -1;
     }
-    env->mstatus |= MSTATUS_VS;
+    env->mstatus |= MSTATUS_VS | MSTATUS_SD;
 #endif
 
     env->vxrm = val;
@@ -320,7 +320,7 @@ static int write_vxsat(CPURISCVState *env, int csrno, 
target_ulong val)
     if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
         return -1;
     }
-    env->mstatus |= MSTATUS_VS;
+    env->mstatus |= MSTATUS_VS | MSTATUS_SD;
 #endif
 
     env->vxsat = val;
@@ -339,7 +339,7 @@ static int write_vstart(CPURISCVState *env, int csrno, 
target_ulong val)
     if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
         return -1;
     }
-    env->mstatus |= MSTATUS_VS;
+    env->mstatus |= MSTATUS_VS | MSTATUS_SD;
 #endif
 
     /*
@@ -362,7 +362,7 @@ static int write_vcsr(CPURISCVState *env, int csrno, 
target_ulong val)
     if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
         return -1;
     }
-    env->mstatus |= MSTATUS_VS;
+    env->mstatus |= MSTATUS_VS | MSTATUS_SD;
 #endif
 
     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
-- 
2.17.1