I found some bugs in target/arm.
The first one is about SVE first-fault or no-fault load/store.
The second is SIMD fcmla(by element).
The third is about CPTR_EL2.
I am not sure I really understand this code. Please confirm the patch set and
let me know if I am wrong.
LIU Zhiwei (4):
target/arm: Fixup special cross page case for sve continuous
load/store
target/arm: Fixup contiguous first-fault and no-fault loads
target/arm: Fixup SIMD fcmla(by element) in 4H arrangement
target/arm: adjust CPTR_EL2 according to HCR_EL2.E2H
target/arm/helper.c | 55 ++++++++++++++++++++++++++++++++++-------
target/arm/sve_helper.c | 42 ++++++++++++++++++++-----------
target/arm/vec_helper.c | 8 ++++++
3 files changed, 82 insertions(+), 23 deletions(-)
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2.23.0
