Re: [PATCH v2 21/28] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN

[Richard Henderson]

On 11/19/20 3:56 PM, Peter Maydell wrote:
> +        } else {
> +            /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */
> +            if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
> +                value &= ~R_V7M_CCR_BFHFNMIGN_MASK;
> +            }

This isn't WI, as you're zeroing the bit not preserving it.
I think you need to merge the current state of the bit to preserve the value
for secure state.


r~