The MIPS3 and MIPS32/64 ISA use different definitions for the CP0 Config0 register.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/mips/cpu.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 23f8c6f96cd..05291cee4db 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -828,7 +828,7 @@ struct CPUMIPSState { #define CP0EBase_WG 11 target_ulong CP0_CMGCRBase; /* - * CP0 Register 16 + * CP0 Register 16 (after Release 1) */ int32_t CP0_Config0; #define CP0C0_M 31 @@ -837,13 +837,20 @@ struct CPUMIPSState { #define CP0C0_MDU 20 #define CP0C0_MM 18 #define CP0C0_BM 16 -#define CP0C0_Impl 16 /* 24..16 */ #define CP0C0_BE 15 #define CP0C0_AT 13 /* 14..13 */ #define CP0C0_AR 10 /* 12..10 */ #define CP0C0_MT 7 /* 9..7 */ #define CP0C0_VI 3 #define CP0C0_K0 0 /* 2..0 */ +/* + * CP0 Register 16 (before Release 1) + */ +#define CP0C0_Impl 16 /* 24..16 */ +#define CP0C0_IC 9 /* 11..9 */ +#define CP0C0_DC 6 /* 8..6 */ +#define CP0C0_IB 5 +#define CP0C0_DB 4 int32_t CP0_Config1; #define CP0C1_M 31 #define CP0C1_MMU 25 /* 30..25 */ -- 2.26.2
