This patchset implements a somewhat miscellaneous collection of new-in-v8.1M features, as well as some bugfixes. It's for-6.0 material.
In the bugfix category: * RAZWI (or BusFault for unprivileged accesses) the whole of the system PPB address range, not just the SCS * Don't clobber ID_PFR1.Security on M-profile * Don't allow VMRS/VMSR to fp sysregs that don't exist on M-profile In the features category: * v8.1M PXN extension * VSCCLRM and CLRM insns * VLDR/VSTR (sysreg) insns * new M-profile fp sysregs: FPSCR_nzcvqc, FPCXT_S, FPCXT_NS * update FPDSCR masking to allow new-in-v8.1M bits in that register As usual, none of this will be enabled until we eventually get to the point of a complete v8.1M implementation and can define a Cortex-M55 CPU model. thanks -- PMM Peter Maydell (15): hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault target/arm: Implement v8.1M PXN extension target/arm: Don't clobber ID_PFR1.Security on M-profile cores target/arm: Implement VSCCLRM insn target/arm: Implement CLRM instruction target/arm: Enforce M-profile VMRS/VMSR register restrictions target/arm: Refactor M-profile VMSR/VMRS handling target/arm: Move general-use constant expanders up in translate.c target/arm: Implement VLDR/VSTR system register target/arm: Implement M-profile FPSCR_nzcvqc target/arm: Use new FPCR_NZCV_MASK constant target/arm: Factor out preserve-fp-state from full_vfp_access_check() target/arm: Implement FPCXT_S fp system register target/arm: Implement FPCXT_NS fp system register hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M include/hw/intc/armv7m_nvic.h | 1 + target/arm/cpu.h | 30 ++ target/arm/m-nocp.decode | 8 +- target/arm/t32.decode | 6 +- target/arm/vfp.decode | 14 + hw/arm/armv7m.c | 2 +- hw/intc/armv7m_nvic.c | 87 ++++- target/arm/cpu.c | 5 +- target/arm/helper.c | 7 +- target/arm/translate.c | 102 ++++-- target/arm/translate-vfp.c.inc | 581 +++++++++++++++++++++++++++++++-- 11 files changed, 765 insertions(+), 78 deletions(-) -- 2.20.1
