From: Bin Meng <[email protected]> This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_gpio model to hw/gpio directory.
Note this also removes the trace-events in the hw/riscv directory, since gpio is the only supported trace target in that directory. Signed-off-by: Bin Meng <[email protected]> --- hw/riscv/trace.h | 1 - include/hw/{riscv => gpio}/sifive_gpio.h | 0 include/hw/riscv/sifive_e.h | 2 +- include/hw/riscv/sifive_u.h | 2 +- hw/{riscv => gpio}/sifive_gpio.c | 2 +- hw/gpio/Kconfig | 3 +++ hw/gpio/meson.build | 1 + hw/gpio/trace-events | 6 ++++++ hw/riscv/Kconfig | 2 ++ hw/riscv/meson.build | 1 - hw/riscv/trace-events | 7 ------- meson.build | 1 - 12 files changed, 15 insertions(+), 13 deletions(-) delete mode 100644 hw/riscv/trace.h rename include/hw/{riscv => gpio}/sifive_gpio.h (100%) rename hw/{riscv => gpio}/sifive_gpio.c (99%) delete mode 100644 hw/riscv/trace-events diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h deleted file mode 100644 index 8c0e3ca..0000000 --- a/hw/riscv/trace.h +++ /dev/null @@ -1 +0,0 @@ -#include "trace/trace-hw_riscv.h" diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h similarity index 100% rename from include/hw/riscv/sifive_gpio.h rename to include/hw/gpio/sifive_gpio.h diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 6374141..b140084 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -21,7 +21,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" -#include "hw/riscv/sifive_gpio.h" +#include "hw/gpio/sifive_gpio.h" #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" #define RISCV_E_SOC(obj) \ diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 936a3bd..fe5c580 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -23,7 +23,7 @@ #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" -#include "hw/riscv/sifive_gpio.h" +#include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c similarity index 99% rename from hw/riscv/sifive_gpio.c rename to hw/gpio/sifive_gpio.c index aac6b44..78bf29e 100644 --- a/hw/riscv/sifive_gpio.c +++ b/hw/gpio/sifive_gpio.c @@ -15,7 +15,7 @@ #include "qemu/log.h" #include "hw/irq.h" #include "hw/qdev-properties.h" -#include "hw/riscv/sifive_gpio.h" +#include "hw/gpio/sifive_gpio.h" #include "migration/vmstate.h" #include "trace.h" diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index 9227cb5..b6fdaa2 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -7,3 +7,6 @@ config PL061 config GPIO_KEY bool + +config SIFIVE_GPIO + bool diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 6bcdfa6..86cae9a 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index c1271fd..6e3f048 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -5,3 +5,9 @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 + +# sifive_gpio.c +sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 +sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 +sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 +sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 76eaf77..5a8335b 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -15,6 +15,7 @@ config SIFIVE_E bool select HART select SIFIVE + select SIFIVE_GPIO select SIFIVE_E_PRCI select UNIMP @@ -23,6 +24,7 @@ config SIFIVE_U select CADENCE select HART select SIFIVE + select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_U_OTP select SIFIVE_U_PRCI diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 2ba4757..24177ef 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events deleted file mode 100644 index 6d59233..0000000 --- a/hw/riscv/trace-events +++ /dev/null @@ -1,7 +0,0 @@ -# See docs/devel/tracing.txt for syntax documentation. - -# hw/gpio/sifive_gpio.c -sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 -sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 -sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 -sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 diff --git a/meson.build b/meson.build index 1e7aee8..66bbb75 100644 --- a/meson.build +++ b/meson.build @@ -706,7 +706,6 @@ if have_system 'hw/watchdog', 'hw/xen', 'hw/gpio', - 'hw/riscv', 'migration', 'net', 'ui', -- 2.7.4
