On 9/1/20 3:38 AM, Bin Meng wrote: > From: Bin Meng <bin.m...@windriver.com> > > Currently the reset vector address is hard-coded in a RISC-V CPU's > instance_init() routine. In a real world we can have 2 exact same > CPUs except for the reset vector address, which is pretty common in > the RISC-V core IP licensing business. > > Normally reset vector address is a configurable parameter. Let's > create a 64-bit property to store the reset vector address which > covers both 32-bit and 64-bit CPUs. > > Signed-off-by: Bin Meng <bin.m...@windriver.com> > Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> > --- > > (no changes since v1) > > target/riscv/cpu.h | 1 + > target/riscv/cpu.c | 1 + > 2 files changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
