Le ven. 28 août 2020 16:26, Richard Henderson <richard.hender...@linaro.org>
a écrit :
> Continue eliminating the sregs array in favor of individual members.
> Does not correct the width of BTR, yet.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
> target/microblaze/cpu.h | 1 +
> target/microblaze/gdbstub.c | 4 ++--
> target/microblaze/helper.c | 4 ++--
> target/microblaze/translate.c | 6 ++++--
> 4 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index bcafef99b0..deddb47abb 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -241,6 +241,7 @@ struct CPUMBState {
> uint64_t ear;
> uint64_t esr;
> uint64_t fsr;
> + uint64_t btr;
> uint64_t sregs[14];
> float_status fp_status;
> /* Stack protectors. Yes, it's a hw feature. */
> diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
> index 2634ce49fc..cde8c169bf 100644
> --- a/target/microblaze/gdbstub.c
> +++ b/target/microblaze/gdbstub.c
> @@ -74,7 +74,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray
> *mem_buf, int n)
> val = env->fsr;
> break;
> case GDB_BTR:
> - val = env->sregs[SR_BTR];
> + val = env->btr;
> break;
> case GDB_PVR0 ... GDB_PVR11:
> /* PVR12 is intentionally skipped */
> @@ -130,7 +130,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t
> *mem_buf, int n)
> env->fsr = tmp;
> break;
> case GDB_BTR:
> - env->sregs[SR_BTR] = tmp;
> + env->btr = tmp;
> break;
> case GDB_PVR0 ... GDB_PVR11:
> /* PVR12 is intentionally skipped */
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index ea290be780..b240dc76f6 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -132,7 +132,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> /* Exception breaks branch + dslot sequence? */
> if (env->iflags & D_FLAG) {
> env->esr |= 1 << 12 ;
> - env->sregs[SR_BTR] = env->btarget;
> + env->btr = env->btarget;
> }
>
> /* Disable the MMU. */
> @@ -160,7 +160,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> if (env->iflags & D_FLAG) {
> D(qemu_log("D_FLAG set at exception bimm=%d\n",
> env->bimm));
> env->esr |= 1 << 12 ;
> - env->sregs[SR_BTR] = env->btarget;
> + env->btr = env->btarget;
>
> /* Reexecute the branch. */
> env->regs[17] -= 4;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index c58c49ea8f..469e1f103a 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1811,7 +1811,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int
> flags)
> "rbtr=%" PRIx64 "\n",
> env->msr, env->esr, env->ear,
> env->debug, env->imm, env->iflags, env->fsr,
> - env->sregs[SR_BTR]);
> + env->btr);
> qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
> "eip=%d ie=%d\n",
> env->btaken, env->btarget,
> @@ -1879,8 +1879,10 @@ void mb_tcg_init(void)
> tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr),
> "resr");
> cpu_SR[SR_FSR] =
> tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr),
> "rfsr");
> + cpu_SR[SR_BTR] =
> + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr),
> "rbtr");
>
> - for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
> + for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
> cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
> offsetof(CPUMBState, sregs[i]),
> special_regnames[i]);
> --
> 2.25.1
>
>
>
