On Fri, 28 Aug 2020, 15:36 Richard Henderson, <[email protected]>
wrote:
> On 8/27/20 10:09 AM, Edgar E. Iglesias wrote:
> > It seems to be getting out of sync when getting a slave-error and the
> core
> > is not setup to take exceptions for slave errors. Looks like a
> pre-existing
> > bug where we're restoring CPU state without taking the exception.
> > The following fixes that particular case in my runs.
> >
> >
> > I'm on a backported QEMU 5.1 so thing may look different in master.
> >
> > diff --git a/target/microblaze/op_helper.c
> b/target/microblaze/op_helper.c
> > index 831ff2cac1..0cae51c2df 100644
> > --- a/target/microblaze/op_helper.c
> > +++ b/target/microblaze/op_helper.c
> > @@ -432,22 +432,19 @@ void mb_cpu_transaction_failed(CPUState *cs,
> hwaddr physaddr, vaddr addr,
> > cpu = MICROBLAZE_CPU(cs);
> > env = &cpu->env;
> >
> > - cpu_restore_state(cs, retaddr, true);
> > - if (!(env->msr & MSR_EE)) {
> > + if (!cpu->cfg.iopb_bus_exception || !(env->msr & MSR_EE)) {
> > return;
> > }
> >
> > + cpu_restore_state(cs, retaddr, true);
> > +
> > env->ear = addr;
> > if (access_type == MMU_INST_FETCH) {
> > - if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
> > - env->esr = ESR_EC_INSN_BUS;
> > - helper_raise_exception(env, EXCP_HW_EXCP);
> > - }
> > + env->esr = ESR_EC_INSN_BUS;
> > + helper_raise_exception(env, EXCP_HW_EXCP);
> > } else {
> > - if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
> > - env->esr = ESR_EC_DATA_BUS;
> > - helper_raise_exception(env, EXCP_HW_EXCP);
> > - }
> > + env->esr = ESR_EC_DATA_BUS;
> > + helper_raise_exception(env, EXCP_HW_EXCP);
> > }
> > }
>
> Thanks for the pointer. I've re-written this section to use
> cpu_loop_exit_restore(), so that the restore is at the end. The new patch
> will
> appear in v2, just before iflags is added to the restore state.
>
>
> r~
>
Ok, cool. I posted another fix to the list (you're on CC) but we can take
your version if it makes it easier. Note that the example I gave you missed
that there's two different props for selecting fetch and data access
faults.
Cheers,
Edgar
>
