On 8/21/20 1:22 AM, David Gibson wrote:
> On Thu, Aug 20, 2020 at 04:01:06PM +0200, Cédric Le Goater wrote:
>> The sPAPR machine has four different IRQ backends, each implementing
>> the XICS or XIVE interrupt mode or both in the case of the 'dual'
>> backend.
>>
>> If a machine is started in P8 compat mode, QEMU should necessarily
>> support the XICS interrupt mode and in that case, the XIVE-only IRQ
>> backend is invalid. Currently, spapr_irq_check() tests the pointer
>> value to the IRQ backend to check for this condition, instead use the
>> 'xics' flag. It's equivalent and it will ease the introduction of new
>> XIVE-only IRQ backends if needed.
>>
>> Signed-off-by: Cédric Le Goater <[email protected]>
>
> Thanks, applied to ppc-for-5.2.
>
> I still kind of want to remove the last vestiges of those
> "backends", but I'm unlikely to have time to do so soon.
What did you have in mind ?
Move the 'xics' and 'xive' flags directly under the spapr machine ?
It would add state.
C.
>
>> ---
>> hw/ppc/spapr_irq.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
>> index 80cf1c3d6bb2..d036c8fef519 100644
>> --- a/hw/ppc/spapr_irq.c
>> +++ b/hw/ppc/spapr_irq.c
>> @@ -172,7 +172,7 @@ static int spapr_irq_check(SpaprMachineState *spapr,
>> Error **errp)
>> * To cover both and not confuse the OS, add an early failure in
>> * QEMU.
>> */
>> - if (spapr->irq == &spapr_irq_xive) {
>> + if (!spapr->irq->xics) {
>> error_setg(errp, "XIVE-only machines require a POWER9 CPU");
>> return -1;
>> }
>
