On Thu, Aug 13, 2020 at 9:00 PM Yifei Jiang <[email protected]> wrote: > > When the cause number is equal to or greater than 23, print "(unknown)" in > trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last > excpetion "guest_store_page_fault" can not be printed. > > In addition, the current check of cause is invalid for riscv_intr_names. So > introduce riscv_cpu_get_trap_name to get the trap cause name. > > Signed-off-by: Yifei Jiang <[email protected]> > Signed-off-by: Yipeng Yin <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 11 +++++++++++ > target/riscv/cpu.h | 1 + > target/riscv/cpu_helper.c | 4 ++-- > 3 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 228b9bdb5d..bcdce85c5e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -96,6 +96,17 @@ const char * const riscv_intr_names[] = { > "reserved" > }; > > +const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) > +{ > + if (async) { > + return (cause < ARRAY_SIZE(riscv_intr_names)) ? > + riscv_intr_names[cause] : "(unknown)"; > + } else { > + return (cause < ARRAY_SIZE(riscv_excp_names)) ? > + riscv_excp_names[cause] : "(unknown)"; > + } > +} > + > static void set_misa(CPURISCVState *env, target_ulong misa) > { > env->misa_mask = env->misa = misa; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index a804a5d0ba..7c72979f6a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -312,6 +312,7 @@ extern const char * const riscv_fpr_regnames[]; > extern const char * const riscv_excp_names[]; > extern const char * const riscv_intr_names[]; > > +const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); > void riscv_cpu_do_interrupt(CPUState *cpu); > int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 75d2ae3434..2e047f0948 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -877,8 +877,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) > } > } > > - trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? > - (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); > + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, > + riscv_cpu_get_trap_name(cause, async)); > > if (env->priv <= PRV_S && > cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { > -- > 2.19.1 > > >
