riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

Richard Henderson Thu, 06 Aug 2020 11:29:23 -0700

On 8/6/20 3:46 AM, [email protected] wrote:
> From: Frank Chang <[email protected]>
> 
> If VS field is off, accessing vector csr registers should raise an
> illegal-instruction exception.
> 
> Signed-off-by: Frank Chang <[email protected]>
> ---
>  target/riscv/csr.c | 5 +++++
>  1 file changed, 5 insertions(+)


Reviewed-by: Richard Henderson <[email protected]>

r~

Re: [RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

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