On Wed, 5 Aug 2020 at 16:26, Richard Henderson <[email protected]> wrote: > > On 8/4/20 12:39 PM, Peter Maydell wrote: > > When a coprocessor instruction in an AArch32 guest traps to AArch32 > > Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields > > which are simply copies of the Rt and Rt2 fields from the trapped > > instruction. However, if the instruction is trapped from AArch32 to > > an AArch64 higher exception level, the Rt and Rt2 fields in the > > syndrome register (ESR_ELx) must be the AArch64 view of the register. > > This makes a difference if the AArch32 guest was in a mode other than > > User or System and it was using r13 or r14, or if it was in FIQ mode > > and using r8-r14. > > > > We don't know at translate time which AArch32 CPU mode we are in, so > > we leave the values we generate in our prototype syndrome register > > value at translate time as the raw Rt/Rt2 from the instruction, and > > instead correct them to the AArch64 view when we find we need to take > > an exception from AArch32 to AArch64 with one of these syndrome > > values. > > > > Fixes: https://bugs.launchpad.net/qemu/+bug/1879587 > > Reported-by: Julien Freche <[email protected]> > > Signed-off-by: Peter Maydell <[email protected]> > > --- > > Reviewed-by: Richard Henderson <[email protected]>
Thanks; applied to master for 5.1. -- PMM
