On Mon, Jul 20, 2020 at 2:48 AM Zong Li <[email protected]> wrote: > > The range of Physical Memory Protection should be from CSR_PMPCFG0 > to CSR_PMPCFG3, not to CSR_PMPADDR9. > > Signed-off-by: Zong Li <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index ac01c835e1..6a96a01b1c 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1353,7 +1353,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MTINST] = { hmode, read_mtinst, write_mtinst > }, > > /* Physical Memory Protection */ > - [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg > }, > + [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg > }, > [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr > }, > > /* Performance Counters */ > -- > 2.27.0 > >
