In contrast to the RFC, add more instructions description. Now it supports RV64IMACFD. Some cross verifications have been done, such as comparison between QEMU and TinyEMU, and comparison between QEMU and C906 FPGA.
Now it has some productive. Features: * support RV64IMACFD. * support multi-precision float point. * support accurate special values generation. Todo: * support RVV and RVP. LIU Zhiwei (11): riscv: Add RV64I instructions description riscv: Add RV64M instructions description riscv: Add RV64A instructions description riscv: Add RV64F instructions description riscv: Add RV64D instructions description riscv: Add RV64C instructions description riscv: Generate payload scripts riscv: Add standard test case riscv: Define riscv struct reginfo riscv: Implement payload load interfaces riscv: Add configure script configure | 4 +- risu_reginfo_riscv64.c | 132 +++++++++ risu_reginfo_riscv64.h | 28 ++ risu_riscv64.c | 47 +++ risugen_riscv.pm | 643 +++++++++++++++++++++++++++++++++++++++++ rv64.risu | 466 +++++++++++++++++++++++++++++ rv64c.risu | 97 +++++++ test_riscv64.s | 85 ++++++ upstream/configure | 204 +++++++++++++ 9 files changed, 1705 insertions(+), 1 deletion(-) create mode 100644 risu_reginfo_riscv64.c create mode 100644 risu_reginfo_riscv64.h create mode 100644 risu_riscv64.c create mode 100644 risugen_riscv.pm create mode 100644 rv64.risu create mode 100644 rv64c.risu create mode 100644 test_riscv64.s create mode 100644 upstream/configure -- 2.23.0
