On Thu, 18 Jun 2020 at 19:08, Richard Henderson <[email protected]> wrote: > > On 6/18/20 3:52 AM, Peter Maydell wrote: > >> + if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, > >> cpu)) { > >> + if (ri->opc1 == 6) { /* SCTLR_EL3 */ > >> + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); > >> + } else { > >> + value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | > >> + SCTLR_ATA0 | SCTLR_ATA); > >> + } > > > > Doesn't SCTLR_EL2 have the same "no ATA0 and no TCF0" that > > SCTLR_EL3 does? > > No. With HCR.{E2H,TGE} = '11', those fields are present.
Ah, right. Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
