On Thu, 21 May 2020 at 20:39, Havard Skinnemoen <hskinnem...@google.com> wrote:
>
> Enough functionality to boot the Linux kernel has been implemented. This
> includes:
>
> - Correct power-on reset values so the various clock rates can be
> accurately calculated.
> - Clock enables stick around when written.
>
> In addition, a best effort attempt to implement SECCNT and CNTR25M was
> made even though I don't think the kernel needs them.
>
> Reviewed-by: Tyrone Ting <kft...@nuvoton.com>
> Signed-off-by: Havard Skinnemoen <hskinnem...@google.com>
Reviewed-by: Joel Stanley <j...@jms.id.au>
> +++ b/hw/misc/npcm7xx_clk.c
> +#define PLLCON_LOKI BIT(31)
> +#define PLLCON_LOKS BIT(30)
> +#define PLLCON_PWDEN BIT(12)
> +
> +static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
Can you add a comment to mention where these come from? If it's the
data sheet, note which version you're using.
> + [NPCM7XX_CLK_CLKEN1] = 0xffffffff,
> + [NPCM7XX_CLK_CLKSEL] = 0x004aaaaa,
> + [NPCM7XX_CLK_CLKDIV1] = 0x5413f855,
> + [NPCM7XX_CLK_PLLCON0] = 0x00222101 | PLLCON_LOKI,
> + [NPCM7XX_CLK_PLLCON1] = 0x00202101 | PLLCON_LOKI,
> + [NPCM7XX_CLK_IPSRST1] = 0x00001000,
> + [NPCM7XX_CLK_IPSRST2] = 0x80000000,
> + [NPCM7XX_CLK_CLKEN2] = 0xffffffff,
> + [NPCM7XX_CLK_CLKDIV2] = 0xaa4f8f9f,
> + [NPCM7XX_CLK_CLKEN3] = 0xffffffff,
> + [NPCM7XX_CLK_IPSRST3] = 0x03000000,
> + [NPCM7XX_CLK_WD0RCR] = 0xffffffff,
> + [NPCM7XX_CLK_WD1RCR] = 0xffffffff,
> + [NPCM7XX_CLK_WD2RCR] = 0xffffffff,
> + [NPCM7XX_CLK_SWRSTC1] = 0x00000003,
> + [NPCM7XX_CLK_PLLCON2] = 0x00c02105 | PLLCON_LOKI,
> + [NPCM7XX_CLK_CORSTC] = 0x04000003,
> + [NPCM7XX_CLK_PLLCONG] = 0x01228606 | PLLCON_LOKI,
> + [NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
> +};
