Version 6 was back in March: https://lists.nongnu.org/archive/html/qemu-devel/2020-03/msg03790.html
Version 7 is a rebase on master, which now contains all prereqs. In addition, two bugs fixed, pointed out by users of the branch. I've done light testing against https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=devel/mte-v4 I still have not implemented the arm,armv8.5-memtag OF property expected by that branch, so I have been disabling it. r~ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b297a37c1b13..b5f18e63f8d1 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -155,6 +155,7 @@ s64 mte_ftr_filter return ID_AA64PFR1_MTE_NI; } +#if 0 /* check the DT "memory" nodes for MTE support */ for_each_node_by_type(np, "memory") { memory_checked = true; @@ -167,6 +168,7 @@ s64 mte_ftr_filter mte_capable = false; return ID_AA64PFR1_MTE_NI; } +#endif return val; } Richard Henderson (42): target/arm: Add isar tests for mte target/arm: Improve masking of SCR RES0 bits target/arm: Add support for MTE to SCTLR_ELx target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT target/arm: Add DISAS_UPDATE_NOCHAIN target/arm: Add MTE system registers target/arm: Add MTE bits to tb_flags target/arm: Implement the IRG instruction target/arm: Implement the ADDG, SUBG instructions target/arm: Implement the GMI instruction target/arm: Implement the SUBP instruction target/arm: Define arm_cpu_do_unaligned_access for user-only target/arm: Add helper_probe_access target/arm: Implement LDG, STG, ST2G instructions target/arm: Implement the STGP instruction target/arm: Restrict the values of DCZID.BS under TCG target/arm: Simplify DC_ZVA target/arm: Implement the LDGM, STGM, STZGM instructions target/arm: Implement the access tag cache flushes target/arm: Move regime_el to internals.h target/arm: Move regime_tcr to internals.h target/arm: Add gen_mte_check1 target/arm: Add gen_mte_checkN target/arm: Implement helper_mte_check1 target/arm: Implement helper_mte_checkN target/arm: Add helper_mte_check_zva target/arm: Use mte_checkN for sve unpredicated loads target/arm: Use mte_checkN for sve unpredicated stores target/arm: Use mte_check1 for sve LD1R target/arm: Add mte helpers for sve scalar + int loads target/arm: Add mte helpers for sve scalar + int stores target/arm: Add mte helpers for sve scalar + int ff/nf loads target/arm: Handle TBI for sve scalar + int memory ops target/arm: Add mte helpers for sve scatter/gather memory ops target/arm: Complete TBI clearing for user-only for SVE target/arm: Implement data cache set allocation tags target/arm: Set PSTATE.TCO on exception entry target/arm: Enable MTE target/arm: Cache the Tagged bit for a page in MemTxAttrs target/arm: Create tagged ram when MTE is enabled target/arm: Add allocation tag storage for system mode target/arm/cpu.h | 36 +- target/arm/helper-a64.h | 16 + target/arm/helper-sve.h | 491 +++++++++++ target/arm/helper.h | 2 + target/arm/internals.h | 148 ++++ target/arm/translate-a64.h | 5 + target/arm/translate.h | 23 +- hw/arm/virt.c | 52 ++ linux-user/aarch64/cpu_loop.c | 7 + linux-user/arm/cpu_loop.c | 7 + target/arm/cpu.c | 77 +- target/arm/cpu64.c | 1 + target/arm/helper-a64.c | 94 +-- target/arm/helper.c | 350 ++++++-- target/arm/mte_helper.c | 897 ++++++++++++++++++++ target/arm/op_helper.c | 16 + target/arm/sve_helper.c | 746 ++++++++++++++--- target/arm/tlb_helper.c | 41 +- target/arm/translate-a64.c | 607 ++++++++++++-- target/arm/translate-sve.c | 1421 ++++++++++++++++++++------------ target/arm/translate-vfp.inc.c | 2 +- target/arm/translate.c | 16 +- target/arm/Makefile.objs | 1 + 23 files changed, 4206 insertions(+), 850 deletions(-) create mode 100644 target/arm/mte_helper.c -- 2.25.1
