On Tue, Mar 17, 2020 at 9:11 AM LIU Zhiwei <[email protected]> wrote: > > Signed-off-by: LIU Zhiwei <[email protected]> > Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/helper.h | 16 +++++++++ > target/riscv/insn32.decode | 5 +++ > target/riscv/insn_trans/trans_rvv.inc.c | 7 ++++ > target/riscv/vector_helper.c | 48 +++++++++++++++++++++++++ > 4 files changed, 76 insertions(+) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 384d661283..abd0bbd2fc 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -826,3 +826,19 @@ DEF_HELPER_6(vfwadd_wf_h, void, ptr, ptr, i64, ptr, env, > i32) > DEF_HELPER_6(vfwadd_wf_w, void, ptr, ptr, i64, ptr, env, i32) > DEF_HELPER_6(vfwsub_wf_h, void, ptr, ptr, i64, ptr, env, i32) > DEF_HELPER_6(vfwsub_wf_w, void, ptr, ptr, i64, ptr, env, i32) > + > +DEF_HELPER_6(vfmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfmul_vf_h, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfmul_vf_w, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfmul_vf_d, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32) > +DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 68e9448842..16fd938261 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -456,6 +456,11 @@ vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 > @r_vm > vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm > vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm > vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm > +vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm > +vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm > +vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm > +vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm > +vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm > > vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm > vsetvl 1000000 ..... ..... 111 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.inc.c > b/target/riscv/insn_trans/trans_rvv.inc.c > index 5ec5debc09..f6864b42bb 100644 > --- a/target/riscv/insn_trans/trans_rvv.inc.c > +++ b/target/riscv/insn_trans/trans_rvv.inc.c > @@ -1910,3 +1910,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) > \ > } > GEN_OPFWF_WIDEN_TRANS(vfwadd_wf) > GEN_OPFWF_WIDEN_TRANS(vfwsub_wf) > + > +/* Vector Single-Width Floating-Point Multiply/Divide Instructions */ > +GEN_OPFVV_TRANS(vfmul_vv, opfvv_check) > +GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check) > +GEN_OPFVF_TRANS(vfmul_vf, opfvf_check) > +GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check) > +GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 16ba9148fb..f5f5897d12 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -3343,3 +3343,51 @@ RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, > vfwsubw16) > RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32) > GEN_VEXT_VF(vfwsub_wf_h, 2, 4, clearl) > GEN_VEXT_VF(vfwsub_wf_w, 4, 8, clearq) > + > +/* Vector Single-Width Floating-Point Multiply/Divide Instructions */ > +RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul) > +RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul) > +RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul) > +GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2, clearh) > +GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4, clearl) > +GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8, clearq) > +RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul) > +RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul) > +RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul) > +GEN_VEXT_VF(vfmul_vf_h, 2, 2, clearh) > +GEN_VEXT_VF(vfmul_vf_w, 4, 4, clearl) > +GEN_VEXT_VF(vfmul_vf_d, 8, 8, clearq) > + > +RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div) > +RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div) > +RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div) > +GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2, clearh) > +GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4, clearl) > +GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8, clearq) > +RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div) > +RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div) > +RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div) > +GEN_VEXT_VF(vfdiv_vf_h, 2, 2, clearh) > +GEN_VEXT_VF(vfdiv_vf_w, 4, 4, clearl) > +GEN_VEXT_VF(vfdiv_vf_d, 8, 8, clearq) > + > +static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s) > +{ > + return float16_div(b, a, s); > +} > + > +static uint32_t float32_rdiv(uint32_t a, uint32_t b, float_status *s) > +{ > + return float32_div(b, a, s); > +} > + > +static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s) > +{ > + return float64_div(b, a, s); > +} > +RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv) > +RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv) > +RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv) > +GEN_VEXT_VF(vfrdiv_vf_h, 2, 2, clearh) > +GEN_VEXT_VF(vfrdiv_vf_w, 4, 4, clearl) > +GEN_VEXT_VF(vfrdiv_vf_d, 8, 8, clearq) > -- > 2.23.0 >
