On Tue, Mar 24, 2020 at 4:20 PM RTOS Pharos <1815...@bugs.launchpad.net> wrote: > > Hi, > > After some debugging (and luck), the problem (at least in the Virt > board) was that the PLIC code inside QEMU addresses the core x 2 instead > of just the core (core=hart). That is why it worked for core 0 (0x2 = 0) > but for core 1 it has to address the PLIC memory area for core 2. > > For example, the interrupt enable address for core 1 starts at offset > 0x002080 (see https://github.com/riscv/riscv-plic-spec/blob/master > /riscv-plic.adoc) but we actually have to change the enable bit for core > 2 (at 0x002100) to make to work for core 1.
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc says: "base + 0x002080: Enable bits for sources 0-31 on context 1" This is context 1, not core 1. It looks to me you were running an image built for SiFive FU540. Please test your image against "sifive_u" machine instead. > > The same is true for the priority threshold and claim complete registers > (we need to multiply the core by 2) > > Either the documentation at https://github.com/riscv/riscv-plic- > spec/blob/master/riscv-plic.adoc does not have the correct memory > addresses for qemu virt board, or qemu appears to be wrong. > > -- Regards, Bin
