On 3/15/20 7:57 PM, LIU Zhiwei wrote:
>> You definitely want to use tcg_gen_gvec_mov (vv), tcg_gen_gvec_dup_i{32,64}
>> (vx) and tcg_gen_gvec_dup{8,16,32,64}i (vi).
> I have a question here.
>
> Are these GVEC IRs proper for any vl, or just when vl equals vlmax?
> I see there are some align assert in these GVEC IR.
Only vl_eq_vlmax. I should have been more precise.
But I expect this boolean to be true quite often.
>
> Now the code is like
>
> static bool trans_vmv_v_v(DisasContext *s, arg_r *a)
> {
> if (vext_check_isa_ill(s, RVV) &&
> vext_check_reg(s, a->rd, false) &&
> vext_check_reg(s, a->rs1, false)) {
>
> if (s->vl_eq_vlmax) {
> tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
> vreg_ofs(s, a->rs1),
> MAXSZ(s), MAXSZ(s));
> } else {
> uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
> static gen_helper_gvec_2_ptr * const fns[4] = {
> gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
> gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
> };
>
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
> }
> return true;
> }
> return false;
> }
>
> Is it right?
Yes, that looks fine.
r~
