Re: [PATCH v5 4/4] target/riscv: add vector configure instruction

[Jim Wilson]

On 2/21/20 1:45 AM, LIU Zhiwei wrote:
+    /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
+    if (a->rs1 == 0) {
+        /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
+        s1 = tcg_const_tl(RV_VLEN_MAX);

This is wrong for the current draft of the vector spec.  x0 now means 
don't change VL.  So this needs to be version specific.

Jim