On Wed, Feb 19, 2020 at 11:54:02AM +1100, David Gibson wrote: > POWER "book S" (server class) cpus have a concept of "real mode" where > MMU translation is disabled... sort of. In fact this can mean a bunch > of slightly different things when hypervisor mode and other > considerations are present. > > We had some errors in edge cases here, so clean some things up and > correct them.
Duh. Forgot to run checkpatch, new version coming shortly.
>
> Changes since v2:
> * Removed 32-bit hypervisor stubs more completely
> * Minor polish based on review comments
> Changes since RFCv1:
> * Add a number of extra patches taking advantage of the initial
> cleanups
>
> David Gibson (12):
> ppc: Remove stub support for 32-bit hypervisor mode
> ppc: Remove stub of PPC970 HID4 implementation
> target/ppc: Correct handling of real mode accesses with vhyp on hash
> MMU
> target/ppc: Introduce ppc_hash64_use_vrma() helper
> spapr, ppc: Remove VPM0/RMLS hacks for POWER9
> target/ppc: Remove RMOR register from POWER9 & POWER10
> target/ppc: Use class fields to simplify LPCR masking
> target/ppc: Streamline calculation of RMA limit from LPCR[RMLS]
> target/ppc: Correct RMLS table
> target/ppc: Only calculate RMLS derived RMA limit on demand
> target/ppc: Streamline construction of VRMA SLB entry
> target/ppc: Don't store VRMA SLBE persistently
>
> hw/ppc/spapr_cpu_core.c | 6 +-
> target/ppc/cpu-qom.h | 1 +
> target/ppc/cpu.h | 25 +--
> target/ppc/mmu-hash64.c | 329 ++++++++++++--------------------
> target/ppc/translate_init.inc.c | 60 ++++--
> 5 files changed, 175 insertions(+), 246 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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