On Tue, 10 Dec 2019 10:38:29 PST (-0800), [email protected] wrote:
On Mon, Dec 9, 2019 at 11:15 PM <[email protected]> wrote:
From: Pan Nengyuan <[email protected]>
Fix a minor memory leak in riscv_sifive_u_soc_realize()
Reported-by: Euler Robot <[email protected]>
Signed-off-by: Pan Nengyuan <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Thanks. This is in the queue, I'm hoping to submit a PR after the H patch set
is ready to go.
Alistair
---
hw/riscv/sifive_u.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0140e95..0e12b3c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_U_PLIC].size);
+ g_free(plic_hart_config);
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
--
2.7.2.windows.1
