On 22/10/2019 15:42, Cédric Le Goater wrote: > Hello, > > On the sPAPR machine and PowerNV machine, the interrupt presenters are > created by a machine handler at the core level and are reseted > independently. This is not consistent and it raises issues when it > comes to handle hot-plugged CPUs. In that case, the presenters are not > reseted. This is less of an issue in XICS, although a zero MFFR could > be a concern, but in XIVE, the OS CAM line is not set and this breaks > the presenting algorithm. The current code has workarounds which need > a global cleanup. > > Extend the sPAPR IRQ backend and the PowerNV Chip class with a new > cpu_intc_reset() handler called by the CPU reset handler and remove > the XiveTCTX reset handler which is now redundant. > > Set the OS CAM line when the interrupt presenter of the sPAPR core is > reseted. This will also cover the case of hot-plugged CPUs.
This series is missing one patch. It needs a resend. C.
