Few of the register writes need not update the spi bus state, so just return after reg write. Added few more dummy register offsets which need the same behaviour.
Signed-off-by: Sai Pavan Boddu <[email protected]> --- Changes for V2: Just skip update of spips cs and fifos Update commit message accordingly Changes for V3: Avoid checking for zynqmp qspi Skip spi bus update for few of the registers hw/ssi/xilinx_spips.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a309c71..c23de47 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ #define R_GPIO (0x30 / 4) #define R_LPBK_DLY_ADJ (0x38 / 4) #define R_LPBK_DLY_ADJ_RESET (0x33) +#define R_IOU_TAPDLY_BYPASS (0x3C / 4) #define R_TXD1 (0x80 / 4) #define R_TXD2 (0x84 / 4) #define R_TXD3 (0x88 / 4) @@ -139,6 +140,8 @@ #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) +#define R_DUMMY_CYCLE_EN (0xC8 / 4) +#define R_ECO (0xF8 / 4) #define R_MOD_ID (0xFC / 4) #define R_GQSPI_SELECT (0x144 / 4) @@ -1022,6 +1025,15 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: + /* Skip SPI bus update for below registers writes */ + switch (addr) { + case R_GPIO: + case R_LPBK_DLY_ADJ: + case R_IOU_TAPDLY_BYPASS: + case R_DUMMY_CYCLE_EN: + case R_ECO: + return; + } xilinx_spips_update_cs_lines(s); xilinx_spips_check_flush(s); xilinx_spips_update_cs_lines(s); -- 2.7.4
