On Thu, 11 Jul 2019 at 11:37, Alex Bennée <[email protected]> wrote: > > When we converted to using feature bits in 602f6e42cfbf we missed out > the fact (dp && arm_dc_feature(s, ARM_FEATURE_V8)) was supported for > -cpu max configurations. This caused a regression in the GCC test > suite. Fix this by setting the appropriate bits in mvfr1.FPHP to > report ARMv8-A with FP support (but not ARMv8.2-FP16). > > Fixes: https://bugs.launchpad.net/qemu/+bug/1836078 > Signed-off-by: Alex Bennée <[email protected]> > Reviewed-by: Richard Henderson <[email protected]> > --- > target/arm/cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index e75a64a25a..ad164a773b 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -2452,6 +2452,10 @@ static void arm_max_initfn(Object *obj) > t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); > cpu->isar.id_isar6 = t; > > + t = cpu->isar.mvfr1; > + t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ > + cpu->isar.mvfr1 = t; > + > t = cpu->isar.mvfr2; > t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ > t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ > -- > 2.20.1
Applied to target-arm.next, thanks. -- PMM
