Patchew URL: https://patchew.org/QEMU/[email protected]/
Hi, This series seems to have some coding style problems. See output below for more information: Message-id: [email protected] Type: series Subject: [Qemu-devel] [PATCH v2 0/4] Miscellaneous patches from the RISC-V fork === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === From https://github.com/patchew-project/qemu * [new tag] patchew/[email protected] -> patchew/[email protected] Switched to a new branch 'test' ea39509 target/riscv: Implement riscv_cpu_unassigned_access e1ca264 disas/riscv: Fix `rdinstreth` constraint 6e119a5 disas/riscv: Disassemble reserved compressed encodings as illegal eb4b804 target/riscv: Fix PMP range boundary address bug === OUTPUT BEGIN === 1/4 Checking commit eb4b80481b1a (target/riscv: Fix PMP range boundary address bug) 2/4 Checking commit 6e119a562b35 (disas/riscv: Disassemble reserved compressed encodings as illegal) ERROR: line over 90 characters #54: FILE: disas/riscv.c:1019: + { "c.addi4spn", rv_codec_ciw_4spn, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz }, ERROR: line over 90 characters #63: FILE: disas/riscv.c:1027: + { "c.addi", rv_codec_ci, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz }, ERROR: line over 90 characters #71: FILE: disas/riscv.c:1030: + { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz }, ERROR: line over 90 characters #72: FILE: disas/riscv.c:1031: + { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, rv_op_lui, rvcd_imm_nz }, ERROR: line over 90 characters #73: FILE: disas/riscv.c:1032: + { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli, rvcd_imm_nz }, ERROR: line over 90 characters #74: FILE: disas/riscv.c:1033: + { "c.srai", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srai, rv_op_srai, rv_op_srai, rvcd_imm_nz }, ERROR: line over 90 characters #75: FILE: disas/riscv.c:1034: + { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi, rvcd_imm_nz }, ERROR: line over 90 characters #84: FILE: disas/riscv.c:1044: + { "c.slli", rv_codec_ci_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_slli, rv_op_slli, rv_op_slli, rvcd_imm_nz }, total: 8 errors, 0 warnings, 100 lines checked Patch 2/4 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/4 Checking commit e1ca26481ca9 (disas/riscv: Fix `rdinstreth` constraint) ERROR: line over 90 characters #24: FILE: disas/riscv.c:617: +static const rvc_constraint rvcc_rdinstreth[] = { rvc_rs1_eq_x0, rvc_csr_eq_0xc82, rvc_end }; ERROR: line over 90 characters #33: FILE: disas/riscv.c:1034: + { "c.andi", rv_codec_cb_imm, rv_fmt_rd_rs1_imm, NULL, rv_op_andi, rv_op_andi, rv_op_andi }, total: 2 errors, 0 warnings, 16 lines checked Patch 3/4 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 4/4 Checking commit ea39509e914c (target/riscv: Implement riscv_cpu_unassigned_access) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/[email protected]/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to [email protected]
