On Tue, 18 Jun 2019 at 16:54, Cédric Le Goater <[email protected]> wrote: > > From: Andrew Jeffery <[email protected]> > > From the datasheet: > > This register stores the current status of counter #N. When timer > enable bit TMC30[N * b] is disabled, the reload register will be > loaded into this counter. When timer bit TMC30[N * b] is set, the > counter will start to decrement. CPU can update this register value > when enable bit is set. > > Signed-off-by: Andrew Jeffery <[email protected]> > Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
