On Thu, 6 Jun 2019 at 18:10, Peter Maydell <[email protected]> wrote: > > Add instruction patterns to cover the "transfer between > Arm core and extension register" spaces (A7.8 and A7.9 > in DDI0406C.c). We omit VMSR/VMRS because they might > have side effects (for stores to special regs) or give > results dependent on previous execution (for loads). > > Signed-off-by: Peter Maydell <[email protected]> > --- > I think these are the only VFP insns we were missing. >
Now pushed to risu master. -- PMM
