On 6/6/19 2:26 AM, Brenken, David (EFS-GH2) wrote:
>>> case OPC2_32_RRPW_INSERT:
>>> - if (pos + width <= 31) {
>>> - tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
>>> - width, pos);
>> Can you explain the problem causing the bug? Deposit looks fine to me.
>> After reading the specs again, I agree that the check needs to be <= 32.
> The bug was recognized because of different behavior between actual hardware
> and QEMU.
> Just from looking at it I would say that deposit masks and then shifts the
> arg2 (D[b]) while the
> manual states to first shift D[b] and then mask it. I remember that it was a
> corner case (e.g.
> width + pos = 31 or 32).
The final two arguments to tcg_gen_deposit_tl are swapped.
It should be pos, width.
r~
