On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> This was res0 before ARMv8.2, but will shortly be used by
> new processor definitions.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu.h | 15 +++++++++++++++
> target/arm/helper.c | 4 ++--
> target/arm/kvm64.c | 2 ++
> 3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index c2899f0bed..02642a7db3 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -855,6 +855,7 @@ struct ARMCPU {
> uint64_t id_aa64pfr1;
> uint64_t id_aa64mmfr0;
> uint64_t id_aa64mmfr1;
> + uint64_t id_aa64mmfr2;
> } isar;
> uint32_t midr;
> uint32_t revidr;
> @@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4)
> FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
> FIELD(ID_AA64MMFR1, XNX, 28, 4)
>
> +FIELD(ID_AA64MMFR2, CNP, 0, 4)
> +FIELD(ID_AA64MMFR2, UAO, 4, 4)
> +FIELD(ID_AA64MMFR2, LSM, 8, 4)
> +FIELD(ID_AA64MMFR2, IESB, 12, 4)
> +FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
> +FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
> +FIELD(ID_AA64MMFR2, NV, 24, 4)
> +FIELD(ID_AA64MMFR2, ST, 28, 4)
> +FIELD(ID_AA64MMFR2, AT, 32, 4)
> +FIELD(ID_AA64MMFR2, IDS, 36, 4)
> +FIELD(ID_AA64MMFR2, FWB, 40, 4)
> +FIELD(ID_AA64MMFR2, TTL, 48, 4)
> +FIELD(ID_AA64MMFR2, BBM, 52, 4)
While we're here:
FIELD(ID_AA64MMFR2, EVT, 56, 4)
FIELD(ID_AA64MMFR2, E0PD, 60, 4)
(from arm v8.5, see
https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64mmfr2_el1
)
otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
