On Fri, Apr 12, 2019 at 2:15 PM Jonathan Behrens <[email protected]> wrote: > > Just to double check, nothing further on this is need from me, right? It is > set to be merged onto the master branch once the 4.0 release is out?
Thanks for checking! Yep you don't need to do anything, Palmer will merge it in the next RISC-V PR after 4.0. Alistair > > Jonathan > > On Wed, Apr 3, 2019 at 7:11 PM Alistair Francis <[email protected]> wrote: >> >> On Mon, Apr 1, 2019 at 1:39 PM Jonathan Behrens <[email protected]> wrote: >> > >> > The 'sfence.vma' instruction is privileged, and should only ever be allowed >> > when executing in supervisor mode or higher. >> > >> > Jonathan >> > >> > Signed-off-by: Jonathan Behrens <[email protected]> >> >> Reviewed-by: Alistair Francis <[email protected]> >> >> Alistair >> >> > --- >> > target/riscv/op_helper.c | 7 ++++--- >> > 1 file changed, 4 insertions(+), 3 deletions(-) >> > >> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c >> > index b7dc18a41e..644d0fb35f 100644 >> > --- a/target/riscv/op_helper.c >> > +++ b/target/riscv/op_helper.c >> > @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env) >> > { >> > RISCVCPU *cpu = riscv_env_get_cpu(env); >> > CPUState *cs = CPU(cpu); >> > - if (env->priv == PRV_S && >> > - env->priv_ver >= PRIV_VERSION_1_10_0 && >> > - get_field(env->mstatus, MSTATUS_TVM)) { >> > + if (!(env->priv >= PRV_S) || >> > + (env->priv == PRV_S && >> > + env->priv_ver >= PRIV_VERSION_1_10_0 && >> > + get_field(env->mstatus, MSTATUS_TVM))) { >> > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); >> > } else { >> > tlb_flush(cs); >> > -- >> > 2.20.1
