On Wed, 13 Mar 2019 at 02:42, gengdongjiu <[email protected]> wrote: > > Add "Reviewed-by" from Richard because Richard has reviewed it in patch > v2[1], thanks. > > Reviewed-by: Richard Henderson <[email protected]> > > [1]: https://www.mail-archive.com/[email protected]/msg604509.html > > On 2019/3/12 20:52, Dongjiu Geng wrote: > > Some generic arch timer registers are Config-RW in the EL0, > > which means the EL0 exception level can have write permission > > if it is appropriately configured. > > > > When VM access registers, QEMU firstly checks whether they have RW > > permission, then check whether it is appropriately configured. > > If they are defined to read only in EL0, even though they have been > > appropriately configured, they still do not have write permission. > > So need to add the write permission according to ARMV8 spec when > > define it. > > > > Signed-off-by: Dongjiu Geng <[email protected]>
Applied to target-arm.next, thanks. -- PMM
